Along with requirements in recent years for electronic parts, such as semiconductor packages to begin with, to be compact, there has been a growing trend toward three-dimensional mounting in which a plurality of electronic parts are laminated to obtain a multilayered semiconductor chip laminated body. Moreover, ongoing research has been conducted to achieve further miniaturization of electronic parts such as a semiconductor chip laminated body.
Consequently, a semiconductor chip, for example, has come to serve as an extremely thin film, and also a fine wiring has been formed in a semiconductor chip. In the semiconductor chip laminated body formed by the three-dimensional mounting, each of the semiconductor chips needs to be laminated horizontally without any damage.
In contrast, there have been conventionally examined a method of protecting wires of a lower semiconductor chip in order to obtain a reliable semiconductor chip laminated body, a method of interposing a spacer chip between semiconductor chips so that the semiconductor chips are horizontally laminated, and the like. As such a method, Patent Document 1, for example, discloses a method of forming spacers in a scattered manner on a face of one semiconductor chip on which the other semiconductor chip is to be laminated, upon laminating a plurality of semiconductor chips, and thereafter laminating the other semiconductor chip.
However, the method of this kind finds it extremely difficult to control the thickness and shape of spacers so as to achieve sufficient miniaturization of a semiconductor chip laminated body and horizontal lamination with a high degree of accuracy. This method also suffers from the problem of complicated processes.
Further, Patent Document 2 discloses a method of laminating dummy chips and spacers between semiconductor chips to be connected, upon laminating a plurality of semiconductor chips.
However, in the semiconductor chip laminated body obtained by such a method, problematically, a large thickness of the entire semiconductor chip laminated body causes difficulty in lowering the height of a package and requires an additional process of laminating dummy chips.
On the other hand, an adhesive containing spacer particles is under investigation.
Patent Document 3, for example, discloses the adhesive having hard plastic fine particles as essential components, the particles having a particle diameter that virtually determines the film thickness after curing the adhesive, and also discloses that silicon elements can be adhered to a lead frame by an adhesive layer having an thickness equivalent to an average particle diameter of the fine particles of 20 μm.
However, even in the case of using the adhesive containing such spacer particles, the problem of a thickness variation of adhesive layers of the obtained laminated body remains to be solved (for example, in Examples of Patent Document 3, the difference between the maximum and minimum thicknesses is as large as 3 to 5 μm), and the mere addition of spacer particles having substantially the same film thickness as the desired film thickness problematically cannot accurately control the film thickness.
Patent Document No. 1: Japanese Kokai Publication 2003-179200;
Patent Document No. 2: Japanese Kokai Publication 2006-66816;
Patent Document No. 3: Japanese Kokai Publication Hei-11-189765